When Hackaday runs a contest, we see all manner of clever projects. But inevitably there are some we don’t see, because their builders didn’t manage to get them finished in time. [Park Frazer]’s phase ...

But taking a voltage-controlled oscillator at 100 MHz (nominal) and dividing its output by 100 will give you a signal you can lock to a 1 MHz crystal oscillator which is, of course, trivial to build.

This application note discusses phase frequency detector characteristics that affect phase-locked loop (PLL) dead band and jitter performance. In PLLs that employ charge pump loop filter designs the ...

The NB4N507A is a fully integrated phase lock loop (PLL) designed to replace expensive crystal oscillators for clock generation in a variety of consumer and networking applications. The IC generates a ...

One of the most challenging tasks in analog circuit design is to adapt a functional block to ever new CMOS process technology. For digital circuits the number of gates per square mm approx. doubles ...

NEC Corporation today announced a development of the "Low-Power Low-Noise All-Digital Phase Lock Loop (ADPLL)" LSI. The newly developed LSI is suitable for midget wireless equipment yielding a long ...

Whilst poring over 4046 phase locked loop data sheets, I noticed yet another subtle useful difference between the the later faster 74HC4046 (diag from NXP data sheet) and the earlier slower CD4046.

The original GPS signals, and indeed most GPS signals including L5, utilize conventional pseudonoise (PN) signal code division multiple access (CDMA), some with both in-phase and quadrature-phase ...