The company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU Instruction Set Architecture (ISA) ...

Benchmarking tool Geekbench has been updated to version 6.4, seeing added support for RISC-V Vector Extensions and Arm Scalable Matrix Extensions. Geekbench is a highly-used benchmark tool, providing ...

RISC-V在AI与高性能计算领域正加速发力，凭借其开源、可扩展、低功耗等特性，逐步从嵌入式设备向数据中心、AI推理等高端场景拓展，并已取得一系列技术突破与生态进展。 在ICCAD2025采访中，阿里巴巴达摩院商务拓展负责人李珏表示，近年来，RISC-V架构快速 ...

9月25日，作为2025北京微电子国际研讨会暨IC WORLD大会的重要专题论坛，RDI生态·北京创新论坛·2025在北京亦庄举行。本次论坛以“挑战·对策·破局·加速”为主题，汇聚产业链上下游代表，围绕RISC-V在垂直场景下的商业化路径及策略展开深度研讨，共同推动RISC-V ...

当地时间 2025 年 10 月 18 日下午，在韩国首尔举办的第 58 届国际微体系结构会议 (IEEE/ACM International Symposium on Microarchitecture, MICRO 2025)学术教程（Tutorial）时段，清华大学集成电路学院何虎老师和其团队成功组织了一场主题为“Ventus: A High-performance Open-source ...

SAN MATEO, Calif.--(BUSINESS WIRE)--SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Dr. Yunsup Lee, CTO of SiFive, and Dr. Krste ...

San Jose, Dec. 07, 2022 (GLOBE NEWSWIRE) -- Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V ...

San Jose, CA, Nov. 06, 2020 (GLOBE NEWSWIRE) -- Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding Premier member ...