IEEE

ASCON-Hash Core with I/O Serialization for Compact Hardware Implementation

Abstract: Ahstract-This paper proposes an I/O-serialized hardware implementation of the permutation core of the NIST-standardized ASCON-Hash: an area-optimized input-output-serialized (IOS) design ...
IEEE

Pipelined Implementation of Secure Hash Algorithm on FPGA for Enhanced Performance

Abstract: This paper presents the implementation and opti-mization of the SHA-256 algorithm on an FPGA platform, specif-ically on the Xilinx Artix-4 DDR board. The main objective is to enhance the ...